Frequency divider with variable modulo

ABSTRACT

The field is that of variable-modulo frequency dividers. To obtain a fast variable-modulo divider over a wide operating range the idea of the invention is to use twin flip-flops ( 1, 2; 3, 4; 5, 6; 7, 8 ) for the feedbacks. The benefit of this configuration is that it avoids the use of decoding gates between the flip-flops this increasing the propagation times of the feedback signals.

The present invention relates to a variable-modulo frequency divider.

It applies in particular to constructions of frequency synthesizers withhigh spectral purity using variable-rank dividers operating at highfrequencies with low modulos.

To construct dividers with low division ranks it is known practice touse commercial synchronous counters of the type for example of thosemarketed under the references 54163 and 10136 respectively by thecompanies registered in the United States TEXAS INSTRUMENTS and MOTOROLAor to use flip-flops linked in cascade according to the diagram of FIG.1 which is that of a divider with two modulos 4 and 5 or else accordingto diagrams adopted in integrated circuits of the type for example ofthat which is marketed under the reference SP8680 by the companyregistered in Britain General Electric Company, or else according topatent application JP-A-63-283316.

However, commercial counters and constructions of dividers by means ofcascaded flip-flops exhibit limited operation within the highfrequencies. This is mainly due, in constructions of the type of thoseof FIG. 1, to the presence of feedback logic gates which increase thepropagation times of the signals between the outputs of the flip-flopsand the feedback input of the first flip-flop.

Other types of construction of dividers of the type of that shown inFIG. 2, which is that of a divider with two modulos 4 and 5, alsoimplement cascaded flip-flops. However, unlike in the case of the modelof FIG. 1, the feedbacks are not achieved by logic gates but by ahard-wired “OR” circuit constructed by simple connections betweenoutputs of flip-flops and the D input of the first flip-flop making itpossible to obviate the propagation times of the signals in the logicgates. This last type of construction makes it possible to obtain higheroperating frequencies than the constructions described previously buthas the drawback of being limited in the number of achievable divisionranks, and in the possible combinations.

Other characteristics and advantages of the invention will becomeapparent with the aid of the following description, given with regard tothe appended drawings which represent:

FIGS. 1 and 2 two embodiments of variable-rank dividers according to theprior art.

FIG. 3 a schematic diagram of an embodiment of a variable-rank divideraccording to the invention (modulo 2 to 10).

FIG. 4 the truth table of a D type flip-flop involved in theimplementation of the diagrams of FIGS. 1, 2, 3, 7A to 7F.

FIG. 5 the timing diagram of the division of rank 5 implementedaccording to the diagram of FIG. 3.

FIG. 6 a control table for the division ranks of the divider of FIG. 3.

FIGS. 7A to 7F simplified embodiments of dividers according to theinvention making it possible to obtain division ranks which can vary byintegers lying between 2 and n; n going from 2 to 7.

The divider according to the invention and which is represented in FIG.3, is more particularly adapted to embodiments in ECL technology wherethe outputs Q and {overscore (Q)} of the flip-flops take place via theemitters of the output transistors, but it may also be adapted to othertechnologies such as TTL technology, for example, to the detriment ofthe speed. It comprises a first chain of D type flip-flops respectivelydenoted 1, 3, 5, 7 and 9 linked in cascade, the output Q of one beinglinked to the D input of the next. Closure of the chain is achieved byconnecting the {overscore (Q)} output of the last flip-flop 9 to the Dinput of the first 1. With each flip-flop 1, 3, 5 and 7 there isassociated respectively a twin flip-flop denoted 2, 4, 6 and 8, theflip-flops of each pair having their D inputs linked together.

The clock inputs C_(K) of the flip-flops are linked together and to theinput F_(e) of the divider.

The {overscore (Q)} outputs of the flip-flops 2, 4, 6, 8 and 9 arelinked together to form a hard-wired “OR” circuit 10. They are fed backto the D input of the flip-flops 1 and 2. Within the framework ofembodiments using TTL logic the {overscore (Q)} outputs must be linkedto a logic “OR” gate with 5 inputs.

The output F_(s) of the divider is constituted by the output Q of theflip-flop 1.

The division ranks are controlled by inputs d₁, d₂, d₃, d₄ and d₅connected respectively to the “SET” inputs denoted S of the flip-flops2, 4, 6, 8 and 9. The division rank obtained as a function of thecontrols d₁ to d₅ is determined according to the table represented inFIG. 6.

To aid the understanding of the diagram every D flip-flop having its Sinput at 1 is disabled and can be ignored. The same holds true for theodd-numbered flip-flops, associated with the even-numbered flip-flops,counted starting from the last even flip-flop in the ascending order oftheir reference number which receives a 0 level on its D input, exceptfor flip-flop 1 which must always be retained since it delivers theoutput signal, and flip-flops 7 and 9 when the S input of flip-flop 9 isat 0.

Thus in the case of division by 5, the flip-flops 2, 8 and 9 can beignored.

Flip-flops 5 and 7 are ignored since the control input d₃ is at zero.The ignored flip-flops are represented dashed in FIG. 3.

The timing diagram for the division by 5 thus carried out is representedin FIG. 5.

In accordance with the array of FIG. 4, the output Q of each flip-floptakes the value of the D input at the moment the clock input C_(K)switches from “0” (low state) to “1” (high state). In the explanation ofthe operation which follows it will be kept in mind that the flip-flopsare synchronous, that is to say that they are controlled by one and thesame clock signal F_(e) arriving at the inputs C_(K).

Initially the outputs Q1, Q3, Q4 and Q6 of flip-flops 1, 3, 4 and 6 areat “0”

Q1 applies a “0” state to inputs D3 and D4 of flip-flops 3 and 4

Q3 applies a “0” state to input D6 of flip-flop 6

The logical “OR” {overscore (Q)}4+{overscore (Q)}6 applies a “1” stateto the input D1 of the first flip-flop 1

On the first rising edge of the clock signal F_(e):

Q1 switches to “1”, implying D3 and D4 at “1”

Q3 remains at “0” implying D6 at “1”

Q4 and Q6 remain at “0”, {overscore (Q)}4+{overscore (Q)}6 implying D1at “1”

On the second rising edge of the clock signal F_(e):

Q1 remains at “1”, implying D3 and D4 at “1”

Q3 and Q4 switch to “1”, Q3 implying D6 at “1”

Q6 remains at “0”, {overscore (Q)}6 implying D1 at “1”

On the third rising edge of the clock signal F_(e):

Q1 remains at “1”, implying D3 and D4 at “1”

Q3 and Q4 remain at “1”, Q3 implying D6 at “1”

Q6 switches to “1”, {overscore (Q)}4+{overscore (Q)}6 implying D1 at “0”

On the fourth rising edge of the clock signal F_(e):

Q1 switches to “0”, implying D3 and D4 at “0”

Q3 and Q4 remain at “1”, Q3 implying D6 at “1”

Q6 remains at “1”, {overscore (Q)}4+{overscore (Q)}6 implying D1 at “0”

On the fifth rising edge of the clock signal F_(e):

Q1 remains at “0” implying D3 and D4 at “0”

Q3 and Q4 drop back to “0”, Q3 implying D6 at “0”, {overscore (Q)}4implying D1 at “1”

Q6 remains at “1”

On the sixth rising edge of the clock signal F_(e):

Q1 rises back to “1”, implying D3 and D4 at “1”

Q3 and Q4 remain at “0”, Q3 implying D6 at “0”,

{overscore (Q)}4 implying D1 at “1”

Q6 drops back to “0”, {overscore (Q)}6 confirming D1 at “1”

At this juncture the divider again has the same states as after thefirst rising edge of the clock signal F_(e) and starts off again for anew identical division cycle.

The division rank of a divider according to the invention is not limitedin theory.

In general, it is possible, by applying the principle of the invention,to construct any divider going from a rank equal to 2 up to a divider ofany rank n>2.

If n is even the number of odd-numbered flip-flops of the first chain isequal to $\frac{n}{2},$

the number of even flip-flops of the second chain is equal to$\frac{n - 2}{2}$

and the {overscore (Q)} outputs of the even flip-flops of the secondchain as well as the last odd-numbered flip-flop of the first chain areconnected together.

If n is odd the number of odd-numbered flip-flops of the first chain isequal to $\frac{n + 1}{2},$

the number of even flip-flops of the second chain is equal to$\frac{n - 3}{2}$

and the {overscore (Q)} outputs of the even-numbered flip-flops of thesecond chain and of the last two odd-numbered flip-flops of the firstchain are connected together.

Another possibility consists when n is odd, in using $\frac{n + 1}{2}$

odd flip-flops in the first chain and $\frac{n - 1}{2}$

even flip-flops in the second chain by linking together the {overscore(Q)} outputs of the even flip-flops and of the last odd-numberedflip-flop of the first chain.

This possibility uses one flip-flop more.

Diagrams of dividers according to the invention for division ranks lyingbetween 2 and n, (n going from 2 to 7) together with their control arrayare represented in FIGS. 7A to 7F.

What is claimed:
 1. Variable-modulo frequency divider of the typecomprising a first chain of n greater than 3 D type flip-flops (1, 3, 5,7, 9) linked in cascade, the output Q of one being linked to the input Dof the next, and in which the complementary output {overscore (Q)} ofthe last flip-flop (9) is fed back to the D input of the first flip-flop(1) by way of an “OR” circuit, characterized in that it comprises asecond chain of D type flip-flops (2, 4, 6, 8) comprising a determinednumber of flip-flops associated respectively with a flip-flop of thefirst chain (1, 3, 5, 7) the flip-flops of each pair thus formed (1, 2;3, 4; 5, 6; 7, 8) having the D inputs linked together, in which thecomplementary outputs {overscore (Q)} of the flip-flops of the secondchain (2, 4, 6, 8) as well as the output {overscore (Q)} of the lastflip-flop of the first chain are linked by the “OR” circuit to the Dinput of the first flip-flop of the first chain and in which controllinks (d₁, d₂ . . . d₅) are provided linking the control inputs S fordisabling the D flip-flops (2, 4, 6, 8) of the second chain and of thelast D flip-flop (9) of the first chain so as to programme the modulo ofthe divider.
 2. Divider according to claim 1, characterized in that itcomprises, for carrying out a division modulo 2 to n even, $\frac{n}{2}$

flip-flops in the first chain and $\frac{n - 2}{2}$

flip-flops in the second chain, the complementary output {overscore (Q)}of the last flip-flop of the first chain and the complementary outputs Qof the flip-flops of the second chain are linked to the D input of thefirst flip-flops of the even and odd chains by way of the “OR” circuit.3. Divider according to claim 1, characterized in that it comprises, forcarrying a division modulo 2 to n odd, $\frac{n + 1}{2}$

flip-flops in the first chain and $\frac{n - 3}{2}$

flip-flops of the second chain, the complementary outputs {overscore(Q)} of the last two flip-flops of the first chain being linked to theoutputs {overscore (Q)} of the flip-flops of the second chain to the Dinput of the first flip-flops of the even and odd chains by way of the“OR” circuit.
 4. Divider according to claim 1, characterized in that itcomprises, for carrying out a division modulo 2 to n odd,$\frac{n + 1}{2}$

odd flip-flops in the first chain and $\frac{n - 1}{2}$

even flip-flops of the second chain, by linking together the outputs{overscore (Q)} of the even flip-flops and of the last odd-numberedflip-flop {overscore (Q)} of the first chain by way of the “OR” circuit.5. Divider according to claim 1 for carrying out a division modulo m ton, m<n, n being as large as desired, characterized by a number offlip-flops which in the truth chart of the divider have their disableinputs S always at zero or altering according to the “0” or “1” state,excluding the flip-flops which have their disable input S always 1.